The controlled introduction of impurities into semiconductor crystals is a key process in solid-state technology, particularly for the fabrication of various electronic and optoelectronic devices, as well as for integrated circuits. Such impurities, when added to modify the electrical, optical, mechanical, or magnetic properties of a material, are referred to as ‘dopants.” The process of introducing dopant impurities into host materials is called ‘doping.’ Although the term ‘impurity’ often has deleterious connotations, the doping of semiconductors with certain impurities at specified concentration levels is an important technology that permits control of properties such as electrical resistivity. In semiconductors, doping is used to form internal junctions that delineate regions that differ both in conductivity and in the dominant type of charge carrier particles (i.e., negatively-charged electrons vs. positively-charged ‘holes’). The junctions between distinctly doped regions of a semiconductor crystal serve as the basis of solid-state devices such as diodes, bipolar and field-effect transistors, laser diodes, detectors, light-emitting diodes, solar cells, and the like.
A common method of impurity doping is ion implantation. In ion implantation processes, and unlike dopant diffusion processes, the target material does not need to be heated to a high temperature. Consequently, ion implantation is compatible with the in-situ coatings used in photoresist-masking and patterning in order to selectively dope defined areas of semiconductor wafers. Nevertheless, ion implanted wafers are often subjected to high-temperature annealing treatments after the ion implantation in order to remove damage to the crystal structure of the wafer caused by the implantation. This post-implantation annealing does not, however, obviate the advantages of ion implantation related to the feasibility of ion implanting photoresist-coated wafers, or wafers that bear structural features such gate and field oxides, and the metal and dielectric layers that are typically encountered with integrated circuits in various stages of fabrication. These coating and delicate features are susceptible to electrostatic charge-induced damage caused by excess charge buildup during the ion implantation process.
The ion implantation process, its application to semiconductor integrated circuits, and equipment used for ion implantation are described and discussed in many texts. The ion implantation process is performed in a vacuum chamber at low pressures. In a typical implementation of ion implantation, gas-phase impurity atoms are ionized, accelerated and focused with an electric and/or magnetic field, and collimated through slits to form either a broad flux or narrow beam of ionized atoms. This ion flux is directed to impinge onto a semiconductor wafer or other type of workpiece. Owing to the energy of the accelerated ionized impurities, the impinging ions penetrate into the target semiconductor material in a statistically predictable fashion. The resulting spatial impurity profile, i.e., impurity concentration as a function of depth beneath the exposed surface of the semiconductor, can be controlled by the energy and dose (total number of ions implanted) of the implantation. The semiconductor wafer is usually masked with patterned films of photoresist or other coating materials such as oxides, nitrides, metals, polysilicon, or polyamide. These protective films, according to their patterning by lithography, either expose or protect subareas of the wafer from penetration by the ion flux or beam. The masking and patterning of masked wafers permits spatially defining the regions of doping by the ion implantation process. Several ion implantation steps, in combination with various masking, patterning, and etching steps, can be used to compose the complex structures of integrated circuits.
Because the implanted dopant ions are electrically charged, a consequence of the ion implantation process is the buildup of electric charge on the wafer workpiece. Actually, the charge imbalance associated with ion implantation is attributed to a number of phenomenon including ejection of secondary electrons and other charged species from the wafer, and absorption of ions from the ambient. As a matter of practice, the charging effects associated with ion implantation are difficult to model. Moreover, the spatial distribution of excess charge will fluctuate over the surface of the wafer because of variations in the dopant ion beam, the variable charging characteristics of the workpiece surface, especially one that is structured with oxides, nitrides, metals, photoresists, and surface regions with different conductivities, and also according to any excess charge already present on the surface of the workpiece. Excess charge distributions will vary over the surface of a wafer, and from wafer to wafer, in a generally unpredictable fashion. To summarize, integrated circuit fabrication entails complex patterned and structured semiconductor wafer surfaces—with regions coated by materials of widely varying charging characteristics and electrical resistance, and it is therefore inevitable that the charge distribution resulting from ion implantation will exhibit much spatial variation over the surface of the workpiece.
It is widely appreciated that charging of a semiconductor device, especially during stages of device fabrication, can be harmful. Excess charge created by the ion implantation process can be troublesome. First, static charges can damage the thin oxide films that are commonly incorporated into semiconductor device structures. These phenomena are generally referred to as ‘arcing’ effects. Second, buildup of excess charge can interfere with the ion implantation process itself or subsequent processing steps. For example, excess charge can repel the impinging beam of ions causing beam divergence, spreading, or ‘blow-up’, resulting in non-uniform implantation and an inhomogeneous dopant distribution.
A simple solution to preventing charge buildup on ion-implanted wafers is to mount the wafer on an electrically conducting platen that is electrically grounded, thus providing a discharge path for excess charge deposited on the wafer during the ion implantation process. Unfortunately, grounding to electrically discharge the workpiece has proven less than completely satisfactory in many instances. The problem of excess charge and the ineffectiveness of grounding to discharge wafers is exacerbated by the use of semiconductor wafers which are of high electrical resistivity, and often are electrically insulating. For instance, many semiconductor device technologies employ sapphire substrates, silicon-on-insulator substrates, semi-insulating compound, semiconductor wafers, and the like which are poor electrical conductors. The performance of many high-speed devices depends on the use of such highly-insulating substrates in order to electrically isolate devices and minimize capacitive coupling effects. For these reasons, other methods of neutralizing excess charge build up during ion implantation, rather than relying on discharging through electrical grounding of the wafer, are needed.
Charge neutralization methods to ameliorate charging effects from ion implantation processes are used in the semiconductor industry, or else have been described or proposed in the patent and/or technical literature. A review of these techniques indicates the scope and importance of this problem for semiconductor technology and serves to highlight some of the technical issues. The need for neutralizing excess charge build up during ion implantation is generally understood and widely appreciated, and as a consequence, several distinct approaches have been developed for such purposes.
One method of charge neutralization is referred to as plasma flooding. In the plasma flooding technique, a plasma, such as an argon plasma, is generated by electrons emitted from a heated filament. The electron-containing plasma is mixed in with the ion beam to partially neutralize the beam and co-deposit compensating electrons along with positively-charged ions of the dopant ion beam on the workpiece.
A second charge neutralization technique is accomplished with an electron gun. In the electron gun method of charge neutralization, an electron beam is created by collimating the electrons emitted by a heated filament. This primary electron beam impinges on a secondary electron target which emits secondary electrons that are then directed onto the wafer to help neutralize the excess charge due to the implanted dopant ions.
A further charge neutralization technique is effected with an electron beam system. This technique uses a large-area lanthanum hexaboride cathode and collection grid to produce a high-current, low-energy electron beam. The electron beam is directed onto a workpiece to neutralize excess charge buildup on the workpiece.
The three methods described above do not allow for spatial variation in the excess charge. Nor do they permit the charge compensation to automatically adjust in response to the variation in excess charge from wafer to wafer. All of the above mentioned methods blanket the workpiece with a fixed amount of compensating charge, irrespective of the spatial details of the excess charge on a particular workpiece. As a result, there is a likelihood of over-compensating the charge on the wafer, thus yielding a wafer with excess negative charge. Further, the use of heated filaments in some of these techniques can be considered a drawback due to the fragility, short lifetime, and proneness to contamination of such filaments. In situations where a plasma is used, the complexity and non-uniformity of the plasma, is disadvantageous.